# clocks
create_clock -name I_osc_25M    -period 40.000 [get_ports I_osc_25M]
create_clock -name I_vin_pclk   -period 6.200 [get_ports I_vin_pclk]
create_clock -name rgmii_p0_rxc -period 8.000 [get_ports rgmii_p0_rxc]
create_clock -name rgmii_p1_rxc -period 8.000 [get_ports rgmii_p1_rxc]

derive_pll_clocks
derive_clock_uncertainty

set sclk *pll|altpll_component|auto_generated|pll1|clk\[0\]
set vin_clk *vin_pclk_pll|altpll_component|auto_generated|pll1|clk\[0\]

create_generated_clock -name rgmii_p0_out_clock -source [get_pins {phy_interface|trans_io_a|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports rgmii_p0_txc]

create_generated_clock -name rgmii_p1_out_clock -source [get_pins {phy_interface|trans_io_b|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports rgmii_p1_txc]

# clock groups
set_clock_groups \
    -asynchronous \
    -group "I_osc_25M" \
    -group "I_vin_pclk" \
    -group "$sclk" \
    -group "rgmii_p0_rxc" \
    -group "rgmii_p1_rxc"

#set_clock_groups \
#    -asynchronous \
#    -group "I_osc_25M" \
#    -group "$vin_clk" \
#    -group "$sclk" \
#    -group "rgmii_p0_rxc" \
#    -group "rgmii_p1_rxc"

# multicycle
set_multicycle_path -from {spi_top:u_spi_top|mcu_decode:u_mcu_decode|O_raddr[*]} -to {regfile:u_regfile|O_cfg_rdata[*]} -setup -end 2
set_multicycle_path -from {spi_top:u_spi_top|mcu_decode:u_mcu_decode|O_raddr[*]} -to {regfile:u_regfile|O_cfg_rdata[*]} -hold -end 1
set_multicycle_path -from {spi_top:u_spi_top|mcu_decode:u_mcu_decode|O_raddr[*]} -to {regfile:u_regfile|O_status_rdata[*]} -setup -end 2
set_multicycle_path -from {spi_top:u_spi_top|mcu_decode:u_mcu_decode|O_raddr[*]} -to {regfile:u_regfile|O_status_rdata[*]} -hold -end 1
set_multicycle_path -from {net_top:u_net_top_p*|net_vob_top:u_net_vob_top|row[*]} -to {net_top:u_net_top_p*|net_vob_top:u_net_vob_top|line_start_addr[*]} -setup -end 2
set_multicycle_path -from {net_top:u_net_top_p*|net_vob_top:u_net_vob_top|row[*]} -to {net_top:u_net_top_p*|net_vob_top:u_net_vob_top|line_start_addr[*]} -hold -end 1

# false path
set_false_path -from {regfile:u_regfile|O_reg_*[*]}
set_false_path -from {vib_top:u_vib_top|vin_fmt_detect:u_vin_fmt_detect|O_video_width[*]}
set_false_path -from {vib_top:u_vib_top|vin_fmt_detect:u_vin_fmt_detect|O_video_height[*]}
set_false_path -to [get_ports sdm1_clk]
set_false_path -to [get_ports sdm2_clk]
set_false_path -from {spi_top:u_spi_top|mcu_decode:u_mcu_decode|op_addr[*]}
set_false_path -from {net_top:u_net_top_p?|reg_px_height[*]}
set_false_path -from {net_top:u_net_top_p?|reg_px_width[*]}
set_false_path -from {net_top:u_net_top_p?|reg_px_start_row[*]}
set_false_path -from {net_top:u_net_top_p?|reg_px_start_col[*]}

set_input_delay -clock [get_clocks {I_vin_pclk}] -min -add_delay 1.1 [get_ports {I_vin_de}]
set_input_delay -clock [get_clocks {I_vin_pclk}] -max -add_delay 5.1 [get_ports {I_vin_de}]
set_input_delay -clock [get_clocks {I_vin_pclk}] -min -add_delay 1.1 [get_ports {I_vin_data[*]}]
set_input_delay -clock [get_clocks {I_vin_pclk}] -max -add_delay 5.1 [get_ports {I_vin_data[*]}]

set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -max 3 [get_ports {rgmii_p0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -max 3 [get_ports {rgmii_p0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -max 3 [get_ports {rgmii_p0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -max 3 [get_ports {rgmii_p0_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -min 1 [get_ports {rgmii_p0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -min 1 [get_ports {rgmii_p0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -min 1 [get_ports {rgmii_p0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p0_rxc}] -min 1 [get_ports {rgmii_p0_rxdv}] -clock_fall -add_delay

set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -max 3 [get_ports {rgmii_p1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -max 3 [get_ports {rgmii_p1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -max 3 [get_ports {rgmii_p1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -max 3 [get_ports {rgmii_p1_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -min 1 [get_ports {rgmii_p1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -min 1 [get_ports {rgmii_p1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -min 1 [get_ports {rgmii_p1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {rgmii_p1_rxc}] -min 1 [get_ports {rgmii_p1_rxdv}] -clock_fall -add_delay

set_false_path -setup -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -setup -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]

set_false_path -setup -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -setup -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]

set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {rgmii_p0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {rgmii_p0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {rgmii_p0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {rgmii_p0_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {rgmii_p0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {rgmii_p0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {rgmii_p0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {rgmii_p0_txd[*]}] -clock_fall -add_delay

set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {rgmii_p1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {rgmii_p1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {rgmii_p1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {rgmii_p1_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {rgmii_p1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {rgmii_p1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {rgmii_p1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {rgmii_p1_txd[*]}] -clock_fall -add_delay

